1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the same and, more particularly, to a device comprising MOS transistors and adjacent gate wires having sidewalls arranged on the walls of said gate wires.
2. Description of the Related Art
MOS transistors having gate wires having sidewalls include an LDD (Lightly Doped Drain) transistor, a DDD (Double Diffused Drain) transistor, and a sidewall transistor.
The following specifically describes methods of manufacturing these MOS transistors.
First, a general process for manufacturing a N-type LDD transistor is described by way of example with reference to FIGS. 5(a)-5(e). FIGS. 5(a)-5(e) show a main sectional view illustrating a general process of manufacturing an N-type LDD transistor.
First, as shown in FIG. 5(a), a field insulation film 502 and a gate insulation film 504 are formed on a P-type semiconductor substrate 501, on which a polycrystalline silicon film 503 having a thickness of 0.4 .mu.m, for example, is grown to provide a gate wiring. Furthermore, a resist 505 is formed on the resultant substrate into a desired pattern by lithography.
Next, as shown in FIG. 5(b), using the resist 505 as a mask, the polycrystalline silicon 503 is etched into a desired shape, after which the resist 505 is removed. Furthermore, shallow N-diffusion layer areas 506 providing source and drain diffusion areas of the N-type LDD transistor are formed, for example, by ion-implanting phosphorous.
The polycrystalline silicon 503 and the gate insulation film 504 function as a gate electrode of a MOS transistor, while the polycrystalline silicon 503 on the field insulation film 502 functions as a signal wire of the MOS transistor.
Next, as shown in FIG. 5(c), an insulation film 507 composed of an oxide film having a thickness, for example, of 0.2 .mu.m is grown over the whole substrate surface.
Then, as shown in FIG. 5(d), the insulation film 507 grown in the preceding process is etched back by anisotropic etching to leave a sidewall of the insulation film 507 on each of the walls of the polycrystalline silicon 503 which functions as a gate wire.
As shown in FIG. 5(e), arsenic, for example, is ion-implanted to form an N.sup.+ diffusion layer area 508 which is deeper than the N.sup.- diffusion layer area 506 to provide the source and drain diffusion layers of the N-type LDD transistor.
The following describes a general process of manufacturing a P-type sidewall transistor as a second example with reference to FIGS. 6(a)-6(e). FIGS. 6(a)-6(e) show a main sectional view illustrating a process of manufacturing the P-type sidewall transistor.
First, as shown in FIG. 6(a), an N-type well area 606 is formed in a P-type semiconductor substrate 601, on which a field insulation film 602 and a gate insulation film 604 are formed. Furthermore, a polycrystalline silicon film 603 having a thickness of 0.4 .mu.m, for example, is grown on the field insulation film 602 and the gate insulation film 604 to provide a gate wire, after which a resist 605 is formed into a desired pattern by lithography.
Next, as shown in FIG. 6(b), with the resist 605 used as a mask, the polycrystalline silicon 603 is etched into a desired shape, after which the resist 605 is removed.
Then, as shown in FIG. 6(c), an insulation film 607 composed of an oxide film having a thickness of 0.2 .mu.m, for example, is grown over the whole substrate surface.
Next, as shown in FIG. 6(d), the insulation film 607 grown in the preceding process is etched back by anisotropic etching to leave a sidewall of the insulation film 607 on each wall of the polycrystalline silicon 603 which functions as a gate wire.
Furthermore, as shown in FIG. 6(e), boron for example is ion-implanted to form P.sup.+ diffusion layer areas 608 to provide the source and drain diffusion layers of the P-type sidewall transistor.
After the above-described manufacturing processes, an inter-layer insulation film, a contact hole, and a metal wiring layer are formed in post-processes on the N-type LDD transistor of FIG. 5 and the P-type sidewall transistor of FIG. 6 by means of techniques well known to these of ordinary skill to fabricate the semiconductor devices.
It is apparent that, in addition to the examples of FIGS. 5(a)-5(e) and FIGS. 6(a)-6(e), if phosphorous is not implanted in the process of FIG. 5(b), an N-type sidewall transistor is formed and, if boron is implanted in the process of FIG. 6(b) to form a shallow P.sup.- diffusion layer area, a P-type LDD transistor is formed.
In yet another example, a diffusion layer area is not implanted before sidewall formation. Rather, at least two ion-implant steps are carried out under different conditions after sidewall formation, to thereby obtain a DDD transistor having a source and drain diffusion layer.
The above-described MOS transistors having sidewalls require, in order to actually form the MOS transistors on a semiconductor substrate, a planar mask pattern design for implementing a desired circuit on the semiconductor substrate. Also, an exposure mask for the lithographic process based on the mask pattern design must also be prepared.
The following describes the above-described mask pattern design using, for example, a 2-input NAND CMOS circuit as shown in FIG. 7.
The 2-input NAND circuit has two P-type MOS transistors MP1 and MP2 and two N-type MOS transistors MN1 and MN2, and receives input signals A and B to output data as an output signal OUT.
As an example of a mask pattern for the above-mentioned 2-input NAND circuit, a mask pattern as shown in FIG. 8 may be used. FIG. 8 shows a top view of such a mask pattern.
The 2-input NAND circuit as shown in FIG. 8 has a P-type diffusion layer area 801 and an N-type diffusion layer area 802. A gate wire 803 to which the input signal A is applied and a gate wire 804 to which the input signal B is applied are formed on the P-type diffusion layer area 801 and the N-type diffusion layer area 802.
More specifically, two P-type MOS transistors formed in the P-type diffusion layer area 801 are connected to each other in parallel with contact holes 805 arranged sandwiching the two gate wires 803 and 804. These contact holes are connected to a metal wiring layer 806 to which supply voltage VCC is applied. At the same time, the two P-type transistors are connected in parallel with contact holes 805 sandwiched between the two gate wires 803 and 804. These contact holes are connected to a metal wiring layer 808 that outputs an output signal OUT.
Two N-type MOS transistors formed in the N-type diffusion layer area 802 in FIG. 8 are connected to each other in series with contact holes 805 arranged to the left of the gate wire 804, and a metal wiring layer 807 to which ground voltage GND is applied. Contact holes 805 arranged to the right of the gate wire 803 are connected with a metal wiring layer 808 to provide an output signal OUT.
The 2-input NAND circuit having the layout pattern shown in FIG. 8 is an example of a design which does not especially consider the area occupied by the transistors and the like.
However, in order to enhance productivity and increase the element packaging density by reducing the size of a semiconductor device, the area occupied by each circuit element and wire must be minimized.
FIG. 9 shows an example of a layout pattern designed from the above viewpoint with respect to the 2-input NAND circuit shown in FIG. 7.
The layout pattern shown in FIG. 9 has a reduced element area as compared with the layout pattern shown in FIG. 8. More specifically, the layout pattern of FIG. 9 uses an arrangement in which the gate wires 903 and 904 of the P-type MOS transistors MP1 and MP2 connected in parallel are bent in the P-type diffusion layer area 901. This reduces the number of contact holes 905, and reduces the size of the P-type diffusion layer area in the lateral direction.
It should be noted that the two gate wires 903 and 904 are connected to a metal wiring layer at a lower left position not shown in the figure via a contact hole. In this example, the position at which the gate wires 903 and 904 are connected to the metal wiring layer is at the lower left of the figure. It will be apparent that the connection may be made at any position depending on the relationship with adjacent elements and wires; for example, positions near the transistor as shown in the figure, away from the same, and the like.
FIG. 10(a) and 10(b) show cross sections of the N-type MOS transistors MN1 and MN2 shown in FIG. 9 obtained by the manufacturing process described with reference to FIGS. 5(a)-5(e). FIG. 10(a) is the cross section along line A--A' of FIG. 9, while FIG. 10(b) is the cross section along line B--B' of FIG. 9. With reference to FIGS. 10(a) and 10(b), parts similar to those previously described in FIG. 5(a)-5(e) are denoted by the same reference numerals.
Referring to FIG. 10(a), if the interval between the adjacent gate wires 903 and 904 is 0.6 .mu.m and the width of the sidewall 507 is 0.2 .mu.m, the width of the sidewall opening in the active area between the two gate wires 903 and 904 is 0.2 .mu.m=0.6 .mu.m-(2.times.0.2 .mu.m). As described above, ion implantation through this 0.2 .mu.m opening forms the N-type diffusion layer area 508.
Conventionally, in designing the pattern of the semiconductor device composed of transistors having the above-described sidewalls, the minimum interval between the gate wires is limited by the ability to expose and develop the resist into a desired shape by lithography and a manufacturing technology for forming the desired wiring by etching with a patterned resist as a mask.
For example, in lithography technology using a g-line, the minimum gate wiring interval is generally about 0.8 .mu.m; in lithography technology using an i-line, the minimum gate wiring interval is generally about 0.6 .mu.m.
The sidewall width is generally about 0.2 .mu.m. The gate wiring width of 0.6 .mu.m and the sidewall width of 0.2 .mu.m in the example of FIGS. 10(a) and 10(b) pose no problem especially.
However, in the development of current semiconductor devices such as semiconductor memory chips, efforts are under way to improve manufacturing techniques for increasing storage capacity while restricting an increase in chip size by reducing the dimensions of the elements constituting the chip and increasing packaging density. As a result, by way of example, the gate wiring interval is made smaller than the conventional 0.6 .mu.m.
On the other hand, the sidewall width cannot be significantly reduced due to factors other than manufacturing technology, such as assuring the reliability of elements by relaxing the electric field at the gate ends of the drain diffusion layer.
In such a situation, designing a gate wiring interval using a pattern design having the minimum dimensions as limited by the manufacturing technology poses several problems.
The following describes these problems in detail with reference to FIGS. 11 through 13.
For example, a manufacturing process in which the gate wiring interval is 0.4 .mu.m and the sidewall width is 0.2 .mu.m, is shown in FIGS. 11(a)-11(c). FIGS. 11(a)-11(c) show the cross section along line A--A' of FIG. 9.
First, as shown in FIGS. 11(a)-11(c), gate wires 903 and 904 are patterned and phosphorous, for example, is implanted to form a shallow N.sup.+ diffusion layer area 506 providing the source/drain diffusion layer of an N-type LDD transistor. Then, an insulation film 507 composed of an oxide film having a thickness of 0.2 .mu.m is grown over the whole surface of the substrate.
The interval between the gate wires 903 and 904 is 0.4 .mu.m and the thickness of the insulation film 507 providing the sidewall is 0.2 .mu.m as described above. Therefore, the active area having an interval of 0.4 .mu.m between the gate wires 903 and 904 is fully covered by the insulation film 507 because the same is grown on the walls of the right and left gate wires to a thickness of 0.2 .mu.m each (which fills in the area between the adjacent gate wires).
Next, as shown in FIG. 11(b), etch back is performed by anisotropic etching to form the sidewalls, but the active area between the gate wires 903 and 904 remains obstructed by the insulation film.
Then, as shown in FIG. 11(c), arsenic, for example, is ion-implanted to form an N.sup.+ diffusion layer area 508 which is a diffusion layer area deeper than an N.sup.- diffusion layer area 506 providing the source/drain diffusion layer of the N-type LDD transistor. Since the active area between the gate wires 903 and 904 is covered and blocked by the insulation film 507, arsenic cannot be implanted into the active area. This results in a diffusion area in this portion composed of only the shallow N.sup.- diffusion layer area 506.
The following describes the above-manufacturing process with reference to FIGS. 12(a) and 12(b) showing the cross section along the line B--B' of FIG. 9.
First, as shown in FIG. 12(a), the gate wires 903 and 904 are patterned and then the insulation film 507 composed of the oxide film having a thickness of up to 0.2 .mu.m is grown over the whole surface of the substrate.
In this case, too, the portion between the two gate wires 903 and 904 is fully covered and blocked by the insulation film 507.
Next, as shown in FIG. 12(b), etch back is performed by anisotropic etching to form the sidewalls, but the portion between the gate wires 903 and 904 remains obstructed by the insulation film 507.
In the examples described with reference to FIGS. 11 and 12, the two gate wires 903 and 904 formed on the field insulation film 502 which function as signal wires do not especially pose any problem.
However, as shown in FIGS. 11(a)-11(c), in the area functioning as a transistor, the active area between the gate wires 903 and 904 is constituted by the N.sup.- diffusion layer area 506. This makes the diffusion layer resistance very high, thereby lowering the transistor performance.
The following describes the above-mentioned manufacturing process along line C--C' of FIG. 9 with reference to FIG. 13.
FIG. 13 shows the cross section of the P-type MOS transistors MP1 and MP2 shown in FIG. 9 along the line C--C'. If the gate wiring interval is 0.4 .mu.m and the sidewall width is 0.2 .mu.m, then, in the sidewall transistor shown in FIGS. 6(a)-6(e), for example, the active area between the gate wires 903 and 904 is covered and blocked by the insulation film 607, so that the active area is not implanted. This poses a fatal problem in that a diffusion layer is not formed and a high performance transistor is not obtained.
These problems are solved in a semiconductor device proposed by Japanese Unexamined Patent Publication No. 5-343419 (hereinafter referred to as a reference example) by way of example.
The above-described reference example proposes to lower the diffusion layer resistance in the source diffusion layer between the gate wires. After the sidewall is formed by a conventional manufacturing process and before ion-implanting, the portion between the gate wires is exposed through a resist mask. The sidewall is further etched back using the resist as a mask to reduce the thickness of the sidewalls arranged between the gate wires, and to thereby enlarge the opening of the active area.
As shown in the reference example, adding the etch back process for partially etching back the sidewall can enlarge the opening of the active area between the gate wires. However, the technique proposed in the reference example is applicable only to the source/diffusion layer between the gate wires from the viewpoint of reliability, and not to a drain diffusion layer to which a voltage is applied.
The technique described in the reference example also poses a problem in that the PR number (number of lithographic steps) is increased by partial etch back of the sidewall.